CodeIEB/🧪 Skills Lab/Grade 11 Theory I — CPU Design, Caching & Storage Hierarchy
Grade 11 Theory
Grade 11 Theory I — CPU Design, Caching & Storage Hierarchy
20 exam-style questions sourced from real IEB Grade 11 past papers and the CodeIEB syllabus notes — including some matching-column (tabulation) questions.
0/20 answered
Question 1
What is multi-processing?
Question 2
What is hyper-threading?
Question 3
Why does a 64-bit register matter compared to a 32-bit register?
Question 4
What is latency, in the context of CPU and RAM performance?
Question 5
Why is SRAM used for processor cache and registers rather than the DRAM used for main RAM?
Question 6
Which cache type stores website files locally so a page loads faster on a repeat visit?
Question 7
Which cache type is shared on a network so multiple users don't need to re-download the same content?
Question 8
What does the System Clock on a motherboard do?
Question 9
What is overclocking?
Question 10
Which bus carries the actual data between the CPU, RAM and chipset?
Question 11
Which external bus is used for high-speed components like graphics cards?
Question 12
In the memory hierarchy (registers, cache, RAM, secondary storage), which general rule holds true?
Question 13
Which criterion in the primary vs secondary storage comparison refers to how much data can be transferred per second?
Question 14
Which memory type is described as non-volatile and generally more reliable for long-term storage?
Question 15
In the Machine Cycle, which step is when the CU retrieves the next instruction from memory?
Question 16
In the Machine Cycle, which step is when the ALU actually performs the operation?
Question 17
What is the difference between multi-tasking and multi-threading?
Question 18
What replaced the older BIOS standard, offering faster boot times and a graphical interface?
Question 19 — Match the columns
Match each term in Column A to its correct definition in Column B.
Column A
Column B
1.
Interrupt
2.
IRQ
3.
CMOS
4.
IO Range
Question 20 — Match the columns
Match each translator type in Column A to its correct description in Column B.